
μ PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A
Read and Write Timing
2.0 Clock Cycles Read Latency
[ μ PD44646092A-A], [ μ PD44646182A-A], [ μ PD44646362A-A]
NOP
READ
READ
NOP
NOP
NOP
WRITE
WRITE
READ
(burst of 2) (burst of 2)
(burst of 2) (burst of 2) (burst of 2)
1
2
3
4
5
6
7
8
9
10
11
TKHKH
K
K#
LD#
R, W#
TKHKL TKLKH
TIVK H
T KHIX
TKHK#H
TK#HKH
TAVKH
TKHAX
Address
ODT state
DQ
A0
ODT-ON
A1
ODT-OFF
A2
A3
A4
ODT-ON
ODT-OFF
ODT state
BW#
QVLD
TCQHQVLD
Read Latency = 2.0 clock cycles
ODT-ON
TCQHQVLD
TKHQV
T KHQV
TKHDX
TKHDX
TKHQ X
T KHQX
TKHQZ
TDVKH
TDVKH
TKHCQX1
DQ
Q00
Q01
Q10
Q11
D20
D21
D30
D31
Q40
Q41
TCQHQX
TCQHQX
CQ
TKHCQV
TKHCQX
TKHCQV
TCQHQV
TCQHQ V
TCQHCQ#H T CQ#HCQH
TKHCQX
CQ#
Remarks 1. Q00 refers to output from address A0.
Q01 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled (high impedance) 3 clock cycles after the last READ (LD# = LOW, R, W# = HIGH)
is input in the sequences of [READ]-[NOP].
3. The third NOP cycle between Read to Write transition may not be necessary for correct device
operation when Read latency = 2.0 clock cycles. However, it may be required to avoid bus contention.
4. When the ODT control pin is LOW or No Connect, the ODT function is always off.
20
Data Sheet M19960EJ2V0DS